Education Class 9

Title: ML-Assisted Hardware Trojan Detection
Instructor: Houman Homayoun, UC Davis

Abstract: With the growth and globalization of IC design and development, there is an increase in the number of Designers/Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no other option but to make use of external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs that are targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan. A Hardware Trojan (HT) can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fall short in detecting HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a novel mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful to help eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this class, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN)-assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods. The following topics will be covered in this class:

  1. Hardware Trojan (HT) taxonomy and overview of state-of-the-art HT detection approaches
  2. Application of Machine Learning (ML) in HT detection
  3. Electronic Design Automation (EDA) flow for automating utilization of ML for HT detection
  4. Demo of an ML-assisted HT detection approach and EDA tool flow
  5. Open Challenges of ML-assisted HT detection

Bio: Houman Homayoun is currently an Associate Professor in the Department of Electrical and Computer Engineering at University of California, Davis. He is also the director of National Science Foundation Center for Hardware and Embedded Systems Security and Trust (CHEST). He conducts research in hardware security and trust, applied machine learning and AI, data-intensive computing and heterogeneous computing, where he has published more than 200 technical papers in the prestigious conferences and journals on the subject and directed over $8M in research funding from NSF, DARPA, AFRL, NIST, US Congress, and various industrial sponsors. His work received several best paper awards and nominations in various conferences including ACM GLSVLSI 2016, IEEE ICDM and ICCAD 2019, ISVLSI 2020, IEEE DCAS 2021. His CHEST center received congressional support for research in HW security which was included in 2021 National Defense Authorization Act. Houman served as Member of Advisory Committee, Cybersecurity Research and Technology Commercialization working group in the Commonwealth of Virginia. He is also serving as core group member of hardware security body of knowledge development team supported by the Department of Defense. He was a recipient of 2010 National Science Foundation computing innovation fellow award by CCC/CRA. Since 2017 he has been serving as an Associate Editor of IEEE Transactions on VLSI. He chaired and co-chaired major conferences in ACM including Great Lake Symposium on VLSI.